1. Field of the Invention
The present invention relates to a capacitor-less memory. In particular, the present invention relates to a capacitor-less memory including a transistor that has both functions of selecting a memory cell and retaining information.
2. Description of the Related Art
For higher integration of a DRAM, so-called capacitor-less DRAM without a capacitor (storage capacitor) to hold charge has attracted attention (see e.g., Reference 1: Japanese Published Patent Application No. 2002-246571, Reference 2: Japanese Published Patent Application No. H8-213624, and Reference 3: Japanese Published Patent Application No. H10-92952). Unlike a conventional DRAM that stores charge in a storage capacitor, a capacitor-less DRAM stores charge in a switching transistor. In the capacitor-less DRAM, since the switching transistor has both functions of selecting a memory cell and retaining information, the storage capacitor is not needed, and thus an area in which elements of a DRAM are formed is decreased, which is advantageous in high integration of a DRAM.
The principle of operation of a capacitor-less DRAM will be described with reference to FIGS. 1, 2A, and 2B. FIG. 1 shows a circuit diagram of one cell of a capacitor-less DRAM. In this example, an n-channel transistor is used.
The writing operation of the capacitor-less DRAM shown in FIG. 1 will be described. First, a voltage which is greater than or equal to a threshold voltage of a transistor 101 is applied to a word line 102, and then the transistor 101 is turned on. Carriers (electrons) are accelerated by an electric field which is generated by application of a positive voltage to a bit line 103, and hot carriers are generated at a drain edge of the transistor 101. The behavior of carriers in the transistor 101 of FIG. 1 is schematically shown in FIG. 2A. The hot carriers which are generated collide with semiconductor atoms (e.g., silicon atoms), so that electrons and holes are newly generated. The generated electrons move to a drain side, and holes move to a substrate side (that is, a side away from a gate electrode) by receiving electric field in a semiconductor active layer. A band structure of bottom of the semiconductor active layer (the substrate side) is shown in FIG. 2B. Here, EF is energy of Fermi level, EC is energy of the bottom of a conduction band, and EV is energy of top of a valence band. The holes which have moved to the bottom of the active layer are trapped between a source and a drain due to a potential barrier ΔEV formed at an interface between the source and the active layer and stored in the bottom of the active layer. In this manner, a threshold voltage of the transistor is decreased when holes are stored in bottom of the active layer, and as a result, current which flows in the transistor at the time of reading a memory is increased. For example, this state can be set to be “1”. In this manner, holes are stored in the bottom of the active layer, so that writing of the memory is performed.
Note that, as described above, since it is necessary to generate hot carriers to write data in a memory, the transistor is operated in a saturation region. That is, when the threshold voltage of the transistor is set to be Vth, the values of a drain voltage Vd (or a bit line voltage) and a gate voltage Vg (or a word line voltage) are set so that (Vd−Vs)>(Vg−Vs)-Vth is satisfied.
Erasing of a memory, that is, writing “0” is performed in such a way that a negative drain voltage is used and then holes are discharged into the drain side. Accordingly, the threshold voltage returns to a state before holes are stored.
As described above, in the capacitor-less DRAM, the threshold voltage of a transistor varies depending on whether the state of the memory is “1” or “0”, and as a result, current which flows in the semiconductor at the time of reading the memory varies. The current is detected by, for example, a sense amplifier, so that whether the state of the memory is “1” or “0” can be determined.
As described above, since the capacitor-less DRAM does not need a storage capacitor, the capacitor-less DRAM has an advantage in high integration of DRAM. However, potential barrier ΔEV on the source side to trap holes in a conventional memory element formed by silicon active layer is not sufficiently high. Therefore, holes stored in the bottom of the active layer surpass the potential barrier ΔEV at a certain ratio and flow to the source side with time (leakage current). This leakage current is proportional to exp(−ΔEV/kBT): (Formula 1, where kB is Boltzmann constant and T is absolute temperature). As a result, the threshold voltage changes and reading error of the memory occurs.
To prevent stored holes (majority carriers) from flowing out, a memory cell including a MOS transistor in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are stacked on a substrate in this order and which has a double heterojunction structure under a channel region is suggested in Reference 3. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer can be a p-type silicon layer, a p-type silicon germanium layer, and a p-type silicon layer, respectively, for example. In this manner, the majority carriers can be prevented from flowing out by trapping the majority carriers in the second semiconductor layer included in the double heterostructure.
However, there is a problem in that three semiconductor layers are needed so as to have a double heterojunction and a structure becomes complicated in the memory cell described in Reference 3.